Generally, multiple times of exposure processes are necessary for semiconductor products in order to form circuit patterns required for operation. For example, in the case of manufacturing a semiconductor product formed of a plurality of layers of the circuit patterns, the exposure processes are necessary to be performed to form holes for connecting the respective layers in addition to the exposure processes to form the respective layers of the circuit patterns. Further, in recent years, double patterning is performed in order to form fine circuit patterns with high density.
In the semiconductor manufacturing, it is important to adjust, within a permissible range, positions of the circuit patterns formed by the multiple times of the exposure processes. In the case where the positions of the circuit patterns cannot be adjusted within the permissible range, proper electric characteristic cannot be obtained and yield is decreased. For this reason, positional deviation of the circuit patterns (overlay) between the respective exposure processes is measured to feed back to an exposure device.
As a method for measuring the overlay, U.S. Pat. No. 7,181,057 (PTL 1) discloses a method, in which a circuit pattern for measurement is formed on a wafer and an image of the pattern for measurement is captured by using an optical microscope, so that the overlay is measured based on a signal waveform obtained from the image. The pattern for measurement is generally formed on a scribe line in the periphery of a semiconductor die because the pattern for measurement needs to have a size approximately several tens of micrometers. Therefore, the overlay cannot be directly measured in a place where the circuit patterns of an actual device (actual patterns) are formed, and it is necessary to estimate the overlay by interpolation or the like. However, due to recent micro-miniaturization in the semiconductor process, the permissible range of the overlay is becoming more reduced and it is difficult to obtain necessary measurement accuracy.
JP 2006-351888 A (PTL 2) and JP 2011-142321 A (PTL 3) disclose methods for measuring the overlay by capturing an image of an actual pattern by using a scanning electron microscope. PTL 2 discloses the method for measuring the overlay, in which contour information of a circuit pattern extracted from the captured image is compared with design information (CAD data) of a semiconductor product. Also, PTL 3 discloses the method for measuring the overlay, in which a relative position between a circuit pattern formed by a first exposure and a circuit pattern formed by a second exposure is calculated, and the relative position is compared with a reference value obtained from the CAD data.